Job Description

The ECE Department at NUS is seeking a Research Fellow to support advanced research in Backside Power Delivery Networks (BS-PDN) and advanced semiconductor packaging. The successful candidate will focus on developing and integrating modeling, co-design, and data-driven optimization methodologies for BS-PDN-enabled systems, including 3DIC and chiplet-based architectures. This position offers an exciting opportunity to work at the forefront of semiconductor technology, with close collaboration across industry partners and academic researchers.

Responsibilities will involve:

1. Research & Development
a.    Conduct cutting-edge research on BS-PDN for advanced logic, chiplet-based, and 3DIC systems.
b.    Develop novel design methodologies, modeling approaches, and optimization techniques for BS-PDN, addressing power integrity, thermal management, and chip–package interaction challenges.
c.    Supervise and mentor junior researchers and graduate students working on BS-PDN design, modeling, and advanced packaging topics.

2. System Integration
a.    Lead the system-level co-design and integration of BS-PDN with package, interposer, and chiplet architectures, including UCIe-based interconnects.
b.    Develop and integrate simulation-driven workflows combining electrical, thermal, and mechanical analyses for BS-PDN-enabled systems.
c.    Drive optimization of BS-PDN layouts, backside vias, redistribution layers, and embedded passives to meet real-world performance and manufacturability requirements

3. Data Analysis & Reporting
a.    Manage the generation, preprocessing, and analysis of large-scale multi-physics simulation and design datasets related to BS-PDN integration.
b.    Validate predictive models and design outcomes against reference simulations and experimental test vehicles.
c.    Prepare technical reports, peer-reviewed publications, and presentations for academic, industrial, and consortium stakeholders.

4. Project Management & Collaboration
a.    Take ownership of technical deliverables and research milestones, ensuring timely execution within project schedules.
b.    Serve as a key technical interface with industry partners (foundries, OSATs, EDA vendors) to align research objectives with industry needs.
c.    Contribute to joint development activities and technology transfer efforts related to BS-PDN adoption.

5. Innovation & Intellectual Property
a.    Drive innovation in BS-PDN architectures, advanced packaging integration, and system co-design methodologies.
b.    Contribute to invention disclosures, patent filings, and technology commercialization activities.
c.    Publish research outcomes in high-impact journals and present at leading semiconductor and packaging conferences.

Qualifications

•    Ph.D. or equivalent degree in Electrical, Electronics, Mechanical, Chemical Engineering, Physics, Material Science or its equivalent from a reputable University/Institute is preferred, or equivalent related experience. 
•    Candidate with experience in microelectronic research, characterisation, metrology and electrical testing, and strong in data analysis will have advantage.
•    Proficiency in data analysis and interpretation using statistical tools and software packages.
•    Excellent communication skills and the ability to work effectively in a collaborative research environment.
•    Motivated and possesses effective communication skills including writing and presenting.
•    Ability to work independently and collaborate within a diverse team.
•    Open to Fixed Term Contract.