Job Description

The ECE Department at NUS is seeking a Senior Research Fellow to support advanced research and provide technical leadership in Backside Power Delivery Networks (BS-PDN) and advanced semiconductor packaging. The successful candidate will play a dual role: spearheading the development of on developing and integrating modeling, co-design, and data-driven optimization methodologies for BS-PDN-enabled systems, including 3DIC and chiplet-based architectures. This position offers an exciting opportunity to work at the forefront of semiconductor technology, with close collaboration across industry partners and academic researchers.

Responsibilities will involve:

1. Research & Development
a.    Lead System-Technology Co-Optimization (STCO) research on BS-PDN for advanced logic, chiplet-based, and 3DIC systems, following UCIe standard.
b.    Define and drive the strategic research roadmap for BS-PDN and advanced packaging initiatives
c.    Develop and integrate simulation-driven workflows combining electrical, thermal, and mechanical analyses for BS-PDN-enabled systems.
d.    Develop novel design methodologies, modeling approaches, and optimization techniques for BS-PDN, addressing power integrity, thermal management, and chip–package interaction challenges.
e.    Manage the generation, preprocessing, and analysis of large-scale multi-physics simulation and design datasets related to BS-PDN integration.
f.    Drive optimization of BS-PDN layouts, backside vias, redistribution layers, and embedded passives to meet real-world performance and manufacturability requirements.
g.    Validate predictive models and design outcomes against reference simulations and experimental test vehicles

2. Leadership & Project Management
h.    Lead, supervise, and mentor junior researchers, postdoctoral fellows, and graduate students, fostering a culture of scientific excellence and collaborative innovation.
i.    Actively contribute to or lead the drafting of research proposals for competitive funding and manage project resources, budgets, and technical allocations effectively.
j.    Serve as a key technical interface with industry partners (foundries, OSATs, EDA vendors) to align research objectives with industry needs.
k.    Contribute to joint development activities and technology transfer efforts related to BS-PDN adoption.

3. Data Analysis & Reporting
l.    Take ownership of technical deliverables and research milestones, ensuring timely execution within project schedules.
m.    Prepare technical reports, peer-reviewed publications, and presentations for academic, industrial, and consortium stakeholders.

5. Innovation & Intellectual Property
n.    Contribute to invention disclosures, patent filings, and technology commercialization activities.
o.    Publish research outcomes in high-impact journals and present at leading semiconductor and packaging conferences.

Qualifications

•    Ph.D. or equivalent degree in Electrical, Electronics, Mechanical, Chemical Engineering, Physics, Material Science or its equivalent from a reputable University/Institute is preferred, or equivalent related experience. 
•    Candidate with experience in microelectronic research, characterisation, metrology and electrical testing, and strong in data analysis will have advantage.
•    Expanded Project Management: Acting as the primary technical interface and taking full ownership of deliverables
•    Proficiency in data analysis and interpretation using statistical tools and software packages.
•    Excellent communication skills and the ability to work effectively in a collaborative research environment.
•    Motivated and possesses effective communication skills including writing and presenting.
•    Ability to work independently and collaborate within a diverse team.
•    Open to Fixed Term Contract.